Design Methodology for Multifunction Vehicle Bus Devices

The specifications analysis for an MVB (Multifunction Vehicle Bus) bus administrator showed that system-on-a-chip strategies should be adopted to cope with its great complexity. Particularly, a new hardware/software codesign methodology has been followed. Its main concept is that the MVB devices (the bus administrator itself and the less complex devices) constitute a “progressive family”. This notion establishes a functional partition that helps to generate the behavioral design: 14 operational blocks and a special memory for the communication data. The whole architecture has been coded in SystemC, not only for verification purposes, but also to set the start point in hardware/software partitioning. After validating this executable description by simulation, estimations about cost and performance in both, hardware and software, have been made. From these, an optimum hardware-software architecture has been obtained. As a result, the electronic platform for the Master device has been generated on an FPGA. Key-Words: Electronic Design methodology, hardware/software partitioning, Train Communication Network, Multifunction Vehicle Bus.